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1 complete current share 10a dc/dc power module ISL8200AM the ISL8200AM is a simple and easy to use high power, current-sharing dc/dc power module for datacom/telecom/ fpga power hungry applications. all that is needed is the ISL8200AM, a few passive comp onents and one vout setting resistor to have a complete 10a design ready for market. the ease of use virtually eliminates the design and manufacturing risks while dramatically improving time to market. need more output current? parallel up to six ISL8200AM modules to scale up to a 60a solution (see figure 6 on page 10). the simplicity of the ISL8200AM is in its "off the shelf", unassisted implementation vers us a discrete implementation. patented current sharing in multi-phase operation greatly reduces ripple currents, bom cost and complexity. for example, parallel 2 for 20a an d up to 6 for 60a. the output voltage can be precisely regulate d to as low as 0.6v with 1% output voltage regulation over line, load, and temperature variations. the ISL8200AM?s thermally enhanced, compact qfn package, operates at full load and over -temperature, without requiring forced air cooling. it's so thin it can even fit on the back side of the pcb. easy access to all pins with few external components, reduces the pcb design to a component layer and a simple ground layer. features ? complete switch mode power supply in one package ? patented current share architecture reduces layout sensitivity when modules are paralleled ? programmable phase shift (1 to 6 phase) ? extremely low profile (2.2mm height) ? input voltage range +3.0v to +20v at 10a, current share up to 60a ? a single resistor sets v out from +0.6v to +6v ? output overvoltage, overcurrent and over-temperature protection and undervoltage indication ? rohs compliant applications ? servers, telecom and datacom applications ? industrial and medical equipment ? point of load regulation related literature ? an1738 ?ISL8200AMeval1phz evaluation board user?s guide? ? isim model - (see respective device information page at www.intersil.com ) complete functional schematic figure 1. complete 10a design, just select r set for the desired v out ISL8200AM package figure 2. the 2.2mm height is ideal for the backside of pcbs when space and height is a premium v in range 3v to 20v v out range 0.6v to 6.0v r set 5k r 1 22 f en vout_set vsen_rem- pvin ISL8200AM power module vin vout ishare iset pgnd pvcc pgnd1 ff r 2 v en 330 f 10 f 1 5 m m 1 5 m m 2.2mm september 13, 2012 fn8271.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL8200AM 2 fn8271.2 september 13, 2012 pinout internal circuit ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL8200AMirz ISL8200AM -40c to +85c 23 ld qfn l23.15x15 notes: 1. add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020 3. for moisture sensitivity level (msl), please see device information page for ISL8200AM . for more information on msl please see techbrief tb363 . pgood clkout ishare_bus isfetdrv fsync_in ph_cntrl vout_set vsen_rem- v cc v cc z comp1 z comp2 vcc r cc pvcc c f1 c f2 pvin r pg vin en ff r clk iset ishare r fs pgnd1 q 1 q 2 c boot1 l out1 r isen-in r os1 r csr c vsen boot 1 ugate 1 phase 1 lgate 1 isen 1a isen 1b v sen1+ v sen1- vout pgnd phase ocset comp fb 1 v mon1 13 12 11 22 8 5 6 10 3 7 15 2 1 20 16 18 19 17 14 21 pgnd1 4 controller r phc 9 v cc c f3 c f4 ldo 5 10k 10k 10k 59k 2.2k 2.2k 330nh internal pgood ISL8200AM module
ISL8200AM 3 fn8271.2 september 13, 2012 pin configuration ISL8200AM (23 ld qfn) top view (22) pgood (23) n.c. (3) isfetdrv (10) ishare_bus (8) clkout (7) fsync_in (12) en (11) ff (13) vin (17) pvin (14) pvcc (15) pgnd1 (18) pgnd (16) phase (20) ocset (5) iset (6) ishare (19) vout (1) vout_set (2) vsen_rem- (9) ph_cntrl (21) vcc (4) pgnd1 pd1 pd3 pd2 pd4 pin descriptions pin # pin name pin description 1 vout_set analog voltage input - used with v out to program the regulator output voltage. the typical input impedance of vout_set with respect to vsen_rem- is 500k . the voltage input typ. is 0.6v. 2 vsen_rem- analog voltage input - this pin is the negative input of standard unity gain operational amplifier for differential r emote sense for the regulator, and should connect to the negative rail of the load/processor. this pin can be used for v out trimming by connecting a resistor from this pin to the vout_set pin. 3 isfetdrv digital output - this pin is used to drive an optional nfet, which will connect ishare with the system ishare bus upon completing a pre-bias startup. the voltage output range is 0v to 5v. 4, 15 pgnd1 normal ground - all voltage levels are referenced to this pad. this pad provides a return path for the low side mosf et drives and internal power circuitries as well as all analog signals. pgnd and pgnd1 should be connected together with a ground plane. 5 iset analog current output - this pin sources a 15a offset cu rrent plus channel 1?s average current. the voltage (viset) set by an external resistor (riset) represents the average current le vel of the local active module . for full-scale current, riset should be ~10k . the output current range is 15a to 126a typ. the iset and ishare pins are used for current sharing purpos es with multiple ISL8200AM modules. in the single module configuration, this pin can be tied to the ishare pin. in mult i-phase operation, if noise is a concern, add an additional 10pf capacitor to the iset line.
ISL8200AM 4 fn8271.2 september 13, 2012 6 ishare analog current output - cascaded system level overcurrent shutdown pin. this pin is used where you have multiple module s configured for current sharing and is us ed with a common current share bus. the bus sums each of the modules' average current contribution to the load to protect for a overcurrent condition at the load. the pin so urces 15a plus average module's output current. the shared bus voltage (v ishare ) is developed across an external resistor (r ishare ). v ishare represents the average current of all active channel(s) that are connected together. the ishare bus voltage is compared with each module's internal reference voltage set by each module's r iset resistor. this will generate an individual current share error signal in each cascaded controller. the share bus impedance r ishare should be set as r iset /nctrl, r iset divided by the number of active current sharin g controllers. the output current from this pin generates a voltage across the external resistor. this voltage, v ishare , is compared to an internal 1.2v threshold for average overcurrent protection. for full-scale current, r ishare should be ~10k . typically 10k is used for r share and r set . the output current range is 15a to 126a typ. 7 fsync_in analog input control pin - an optional external resistor (rfs-ext) connected to this pin and ground will increase the oscillator switching frequency. it has an internal 59k resistor for a default frequency of 700khz. the internal oscillator will lock to an external frequency source when connected to a square waveform . the external source is typically the clkout signal from another ISL8200AM or an external clock. the internal oscillator synchronizes with the leading positive edge of the input signal. the input voltage range for the external source is 0v to 5v square wave. when not synchronized to an external clock, a 100pf capacitor between fsync_ in and pgnd1 is recommended. 8 clkout digital voltage output - this pin provides a clock signal to synchronize with other ISL8200AM(s). when there is more tha n one ISL8200AM in the system, the two independent regulators can be programmed via ph_cntrl for different degrees of phase delay. 9 ph_cntrl analog input - the voltage level on this pin is used to program the phase shift of the clkout clock signal to synchro nize with other module(s). 10 ishare_bus open pin until first pwm pulse is generated. then, vi a an internal fet, this pin connects the module?s ishare to th e system?s ishare bus after pre-bias is complete and soft-start is initiated. 11 ff analog voltage input - the voltage on this pin is fed into the controller, adjusting the sawtooth amplitude to generate the feed-forward function. the input voltage range is 0.8 to v cc . typically, ff is connected to en. 12 en this is a double function pin: analog input voltage - the input voltage to this pin is comp ared with a precision 0.8v reference and enables the digital soft-start. the input voltage range is 0v to v cc or v in through a pull-up resistor maintaining a typical current of 5ma. analog voltage output - this pin can be used as a voltage moni tor for input bus undervoltage lockout. the hysteresis levels of the lockout can be programmed via this pin using a resistor di vider network. furthermore, during fault conditions (such as overvoltage, overcurrent, and over-temperature), this pin is us ed to communicate the information to other cascaded modules by pulling the wired or low as it is an open drain. the output voltage range is 0v to v cc . 13 vin analog voltage input - this pin should be tied directly to the input rail when using the internal linear regulator. it pro vides power to the internal linear drive circuitry. when used with an external 5v supply, this pin should be tied directly to pvcc. t he internal linear device is protected against the reversed bias generated by the remaining charge of the decoupling capacitor at vcc when losing the input rail. the input voltage range is 4.5v to 20v. 14 pvcc analog output - this pin is the output of the internal seri es linear regulator. it provides the bias for both low-side an d high-side drives. its operational voltage range is 4.5v to 5.5v. th e decoupling ceramic capacitor in the pvcc pin is 10f. 16 phase analog output - this pin is the phase node of the regulator. the output voltage range is 0v to 30v. 17 pvin analog input - this input voltage is applied to the power fe ts with the fet?s ground being the pgnd pin. it is recommende d to place input decoupling capacitance, 22f, directly between the pvin pin and the pgnd pin as close as possible to the module. the input voltage range is 3v to 20v. 18 pgnd all voltage levels are referenced to this pad. this is the low side mosfet ground. pgnd and pgnd1 should be connected together with a ground plane. 19 vout output voltage from the module. the output voltage range is 0.6v to 6v. 20 ocset analog input - this pin is used with the phase pin to set the current limit of the module. the input voltage range is 0v to 30v. 21 vcc analog input - this pin provides bias power for the analog ci rcuitry. it?s operational range is 4.5v to 5.5v. in 3.3v appl ications, vcc, pvcc and vin should be shorted to allow operat ion at the low end input as it relates to the v cc falling threshold limit. this pin can be powered either by the internal li near regulator or by an external voltage source. 22 pgood analog output - this pin, pu lled up to vcc via an internal 10k ? resistor, provides a power good signal when the output is within 9% of nominal output regulation point with 4% hysteresis (13%/9%), and soft-start is complete. an external pull-up is not required. pgood monitors the outputs (v mon1) of the internal differential amplifiers. the output voltage range is 0v to v cc . pin descriptions (continued) pin # pin name pin description
ISL8200AM 5 fn8271.2 september 13, 2012 23 nc not internal connected pd1 phase thermal pad used for both the phase pin (pin # 16) and fo r heat removal connecting to heat dissipation layers using via s. connect this pad to a copper island on the pcb board with the same shape as the pad; this is electrically connected to phase pin 16. pd2 pv in thermal pad used for both the pvin pin (pin # 17) and for heat removal connecting to heat dissipation layers using vias. connec t this pad to a copper island on the pcb board with the same shape as the pad; this is electrically connected to pvin pin 17. pd3 pgnd thermal pad used for both the pgnd pin (pin # 18) and fo r heat removal connecting to heat dissipation layers using vias . connect this pad to a copper island on the pcb board with the same shape as the pad; this is electrically connected to pgnd pin 18. pd4 v out thermal pad used for both the vout pin (pin # 19) and for heat removal connecting to heat di ssipation layers using vias. conne ct this pad to a copper island on the pcb board with the same shape as the pad; this is electrically connected to vout pin 19. pin descriptions (continued) pin # pin name pin description typical application circuits figure 3. single phase 10 a 1.2v output circuit isfetdrv ishare_bus clkout fsync_in en ff vin pvin pvcc pgnd1 pgnd phase ocset iset ishare vout vout_set vsen_rem- pgood ph_cntrl vcc ISL8200AM vout pgood isfetdrv1 c3 r1 r2 c203 c211 rishare1 c209 rset c9 vcc pvin ground vout ground 270f 8.25k 2.05k 22f 1nf 2.2k 330f 10f 5k set r1 and r2 such that 0.8v ven 5.0v rset can change vout do not tie en directly to a power source refer to table 1
ISL8200AM 6 fn8271.2 september 13, 2012 typical application circuits (continued) figure 4. two phase 20a 3.3v output circuit isfetdrv ishare_bus clkout fsync_in en ff vin pvin pvcc pgnd1 pgnd phase ocset iset ishare vout vout_set vsen_rem- pgood ph_cntrl vcc ISL8200AM isfetdrv ishare_bus clkout fsync_in en ff vin pvin pvcc pgnd1 pgnd phase ocset iset ishare vout vout_set vsen_rem- pgood ph_cntrl vcc ISL8200AM vout vout pgood pgood isfetdrv1 isfetdrv2 c3 r1 r2 c203 c211 c303 c311 rishare1 riset1 c209 rset1 rset2 riset2 c309 c9 vcc2 vcc1 pvin ground vout ground 270f 26.7k 2.61k 22f 1nf 22f 1nf 10k 10f 10k 10k 100f (x6) 10f 10k 5k ishare ishare 2.2nf 2.2nf
ISL8200AM 7 fn8271.2 september 13, 2012 absolute maximum rating s thermal information input voltage, pvin, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +27v driver bias voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v signal bias voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v boot/ugate voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +36v phase voltage, v phase . . . . . . . . . . . . . . . . . . . v boot - 7v to v boot + 0.3v boot to phase voltage, v boot - v phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc + 0.3v input, output or i/o voltage . . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc + 0.3v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v charge device model (tested per jesd22-c101c). . . . . . . . . . . . . . . 1kv latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) qfn package (notes 4, 5) . . . . . . . . . . . . . . 13 2.0 maximum storage temperature range . . . . . . . . . . . . . .-55c to +150c recommended operating conditions input voltage, pvin, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 20v driver bias voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3v to 5.6v signal bias voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3v to 5.6v boot to phase voltage v boot - v phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <6v industrial ambient temperature range . . . . . . . . . . . . . . . -40c to +85c junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board (i.e., 4-layer type wit hout thermal vias - see tech brief tb379 ) per jedec standards except that the top and bottom layers assume solid plains. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside . electrical specifications boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 7) typ (note 6) max (note 7) units vcc supply current nominal supply v in current i q_vin pvin = v in = 20v; no load; f sw = 700khz 36 ma nominal supply v in current i q_vin pvin = v in = 4.5v; no load; f sw =700khz 27 ma shutdown supply v cc current i vcc en = 0v, v cc = 2.97v 9 ma internal linear regulator maximum current i pvcc pvcc = 4v to 5.6v 320 ma saturated equivalent impedance r ldo p-channel mosfet (v in = 5v) 1 ? pvcc voltage level (note 7) pvcc i pvcc = 0ma, v in = 12v 5.15 5.4 5.60 v power-on reset (note 7) rising vcc threshold 2.85 2.97 v falling vcc threshold 2.65 2.75 v rising pvcc threshold 2.85 2.97 v falling pvcc threshold 2.65 2.75 v system soft-start delay t ss_dly after pll, v cc , and pvcc pors, and en above their thresholds 384 cycles enable (note 7) turn-on threshold voltage 0.75 0.8 0.86 v hysteresis sink current i en_hys 21 30 35 a undervoltage lockout hysteresis v en_hys v en_rth = 10.6v; v en_fth = 9v r up = 53.6k ? , r down = 5.23k ? 1.6 v sink current i en_sink ven = 1v 15.4 ma sink impedance r en_sink ven = 1v 64 ? oscillator oscillator frequency fosc r fs = 59k ? ; figure 34 700 khz total variation (note 7) v cc = 5v; -9 +9 %
ISL8200AM 8 fn8271.2 september 13, 2012 frequency synchronization and phase lock loop (note 7) synchronization frequency v cc = 5.4v fosc 1500 khz pll locking time v cc = 5.4v; f sw = 700khz 210 s input signal duty cycle range 10 90 % pwm (note 7) minimum pwm off time t min_off 310 345 410 ns current sampling blanking time t blanking 175 ns output characteristics output continuous current range i out(dc) pvin = v in = 12v, v out = 1.2v 0 10 a line regulation accuracy v out / v in v out = 1.2v, i out = 0a, pvin = v in = 3.5v to 20v 0.15 % v out = 1.2v, i out = 10a, pvin = v in = 5v to 20v 0.15 % load regulation accuracy v out / i out i out = 0a to 10a, v out = 1.2v, pvin = v in = 12v 0.1 % output ripple voltage v out i out = 10a, v out = 1.2v, pvin = v in =12v 27 mv p-p i out = 0a, v out = 1.2v, pvin = v in = 12v 19 mv p-p dynamic characteristics voltage change for positive load step v out-dp i out = 0a to 5a. current slew rate = 2.5a/s, pvin = v in = 12v, v out = 1.2v 45 mv p-p voltage change for negative load step v out-dn i out = 5a to 0a. current slew rate = 2.5a/s, pvin = v in = 12v, v out = 1.2v 55 mv p-p reference (note 7) reference voltage (include error and differential amplifiers? offsets) v ref 0.6 v -0.75 0.75 % differential amplifier (note 7) dc gain ug_da unity gain amplifier 0 db unity gain bandwidth ugbw_da 5 mhz v sen+ pins input current i vsen+ 0.2 1.16 2.5 a maximum source current for current sharing i vsen1- vsen1- source current for current sharing when parallel multiple modules each of which has its own voltage loop 350 a input impedance r vsen+ _to _vsen- v vsen+ /i vsen+ , v vsen+ = 0.6v -500 k ? output voltage swing 0 v cc - 1.8 v input common mode range -0.2 v cc - 1.8 v disable threshold v vsen- v mon1 = tri-state v cc - 0.4 v overcurrent protection (note 7) channel overcurrent limit i source v cc = 2.97v to 5.6v 111 a channel overcurrent limit i source v cc = 5v; 89 111 129 a share pin oc threshold v oc_ishare comparator offset included 1.16 1.20 1.22 v current share external current share accuracy up to 3 phases 10 % power good monitor (note 7) undervoltage falling trip point v uvf percentage below reference point -15 -13 -11 % undervoltage rising hysteresis v uvr_hys percentage above uv trip point 4 % overvoltage rising trip point v ovr percentage above reference point 11 13 15 % electrical specifications boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 7) typ (note 6) max (note 7) units
ISL8200AM 9 fn8271.2 september 13, 2012 overvoltage falling hysteresis v ovf_hys percentage below ov trip point 4 % pgood low output voltage i pgood = 2ma 0.35 v sinking impedance i pgood = 2ma 70 ? maximum sinking current v pgood < 0.8v 10 ma overvoltage protection (note 7) ov latching trip point en = ugate = latch low, lgate = high 118 120 122 % ov non-latching trip point en = low, ugate = low, lgate = high 113 % lgate release trip point en = low/high, ugate = low, lgate = low 87 % over-temperature protection controller junction temperature over-temperature trip 150 c over-temperature release threshold 125 c internal component values internal resistor between pvcc and vcc pin r cc 5 ? internal resistor between phase and ocset pins r isen-in 2.2k ? internal resistor between fsync_in and pgnd1 pins r fs 59k ? internal resistor between pgood and vcc pins r pg 10k ? internal resistor between clkout and vcc pins r clk 10k ? internal resistor between ph_cntrl and vcc pins r phc 10k ? internal resistor between vout_set and vsen_rem- pin r os1 2.2k ? notes: 6. parameters with typ limits are not prod uction tested, unless otherwise specified. 7. parameters with min and/or max limits are 100% tested for internal ic prior to module assembly, unless otherwise specified. t emperature limits established by characterization and are not production tested. electrical specifications boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 7) typ (note 6) max (note 7) units
ISL8200AM 10 fn8271.2 september 13, 2012 isfetdrv ishare_bus clkout fsync_in en ff vin pvin pvcc pgnd1 pgnd phase ocset iset ishare vout vout_set vsen_rem- pgood ph_cntrl vcc ISL8200AM vout isfetdrv1 c3 r1 r2 c203 c211 rishare1 c209 rset c9 vcc pvin ground vout ground 270f 16.5k 4.12k 22f 1nf 2.2k 47f (x8) 10f 5k c205 10nf figure 5. test circuit for all performance and derating graphs refer to table 1 for rset vs. vout vout = 1.2v for rset = 2.2k typical performance characteristics efficiency performance t a = +25c, pv in = v in , c in = 220fx1, 10f/ceramic x 2, c out = 47f/ceramic x 8. figure 6. efficiency vs load current (5v in ) figure 7. efficiency vs load current (12v in ) figure 8. efficiency vs load current (20v in ) figure 9. 1.2v transient response 60 65 70 75 80 85 90 95 100 0610 load current (a) efficiency (%) 2.5v 1.5v 1.2v 0.8v 24 8 3.3v 60 65 70 75 80 85 90 95 100 load current (a) efficiency (%) 5.0v 0610 24 8 2.5v 1.5v 1.2v 0.8v 3.3v 60 65 70 75 80 85 90 95 100 load current (a) efficiency (%) 5.0v 0610 2.5v 1.5v 1.2v 24 8 3.3v v in = 12v v out = 1.2v i out = 0a to 5a v out
ISL8200AM 11 fn8271.2 september 13, 2012 typical performance characteristics (continued) transient response performance t a = +25c, pv in = v in = 12v, c in = 220fx1, 10f/ceramic x 2, c out = 47f/ceramic x 8 i out = 0a to 5a, current slew rate = 2.5a/s figure 10. 1.5v transient response figure 11. 1.8v transient response figure 12. 2.5v transient response figure 13. 3.3v transient response figure 14. four module clock sync (v in = 12v) v in = 12v v out = 1.5v i out = 0a to 5a v out v in = 12v v out = 1.8v i out = 0a to 5a v out v in = 12v v out = 2.5v i out = 0a to 5a v out v in = 12v v out = 1.8v i out = 0a to 5a v out phase1-m phase2-m phase3-m phase4-s
ISL8200AM 12 fn8271.2 september 13, 2012 typical performance characteristics (continued) output ripple performance t a = +25c, pv in = v in = 12v, c in = 220fx1, 10f/ceramic x 2, c out = 100f/ceramic x 6 i out = no load , 5, 10a figure 15. overcurrent protection figure 16. 50% pre-bias start up figure 17. 1.2v output ripple figure 18. 1.5v output ripple figure 19. 2.5v output ripple figure 20. 3.3v output ripple phase v out en v in = 0v to 18v v out = 1.2v i out = no load phase v out pgood pvin v out 5a v out 10a v out no load v out 10a v out 5a v out no load v out 10a v out 5a v out no load v out 10a v out 5a v out no load
ISL8200AM 13 fn8271.2 september 13, 2012 applications information programming the output voltage (r set ) the ISL8200AM has an internal 0.6v 0.7% reference voltage. programming the output voltage requires a dividing resistor (r set ) between the vout_set pin and the v out regulation point. the output voltage can be calcul ated as shown in equation 1: note: ISL8200AM has integrated 2.2k ? resistances into the module dividing resistor for the bottom side (r os ). the resistances for different output voltages in single phase operation are listed in table 1. for a parallel setup, please refer to the current sharing application note ( coming soon ). the output voltage accuracy can be improved by maintaining the impedance at v outset (internal v sen1+ ) at or below 1k ? effective impedance. note: the impedance between v sen1+ and v sen1- is about 500k . the module has a minimum input voltage at a given output voltage, which needs to be a minimum of 1.43 times the output voltage if operating at f sw = 700khz switching frequency. this is due to the minimum pwm off time (t min-off ). the equation to determine the minimum pv in to support the required v out is given by equations 2 and 3; it is recommended to add 0.5v to the result to account for temperature variations. t sw = switching period = 1/f sw for the 700khz switching frequency = 1428ns for 3.3v input voltage operation, the vin voltage is recommended to be 5v for sufficient gate drive voltage. this can be accomplished by using a voltage greater than or equal to 5v on vin, or directly connecting the 5v source to both vin and pvcc. vin is the input to the internal ldo that powers the control circuitry while pvcc is the output of the aforementioned ldo. pvin is the power input to the power stage. figure 21 shows a scenario where the power stage is running at 3.3v and the control circuitry is running at 5.0v; keep in mind that the pvcc pin is also at 5.0v to ensure that the ldo is not functioning. figure 22 shows a setup where both the control circuitry and the power stage is at a 5.0v rail. it is imperative to not cross 5.5v in this setup as that is the voltage limit on the pvcc pin. figure 23 is a more general setup and can accommodate vin ranges up to 20v; pvcc is not tied to vin and hence the control circuitry is powered by the internal ldo. the circuit shown in figure 24 en sures proper startup by injecting current into the ishare line unti l all phases are ready to start regulating. table 1. v out - r set v out 0.6v 0.8v 1.0v 1.2v r set 0 ? 732 ? 1.47k ? 2.2k ? v out 1.5v 1.8v 2.0v 2.5v r set 3.32k ? 4.42k ? 5.11k ? 6.98k ? v out 3.3v 5.0v 6.0v r set 10k ? 16.2k ? 20k ? v out 0.6 1 r set r os ------------ - + ?? ?? ?? = (eq. 1) pv in_min v out t sw t sw t min_off ? --------------------------------------- = (eq. 2) pv in_min 1.43 v out = (eq. 3) figure 21. 3.3v operation v in = 5.0v v out r set 5k r 1 c in2 en vout_set vsen_rem- pvin ISL8200AM power module vin vout ishare iset pgnd pvcc pgnd1 ff r 2 v en p vcc = 5.0v c out 10f p vin = 3.3v c in1 v in = 5.0v v out r set 10f 5k r 1 en vout_set vsen_rem- pvin ISL8200AM power module vin vout ishare iset pgnd pvcc pgnd1 ff r 2 v en p vcc = v in c in c out do not cross 5.5v figure 22. 5.0v operation v in = 5v-20v v out r set 10f 5k r 1 en vout_set vsen_rem- pvin ISL8200AM power module vin vout ishare iset pgnd pvcc pgnd1 ff r 2 v en c out c in figure 23. 5v to 20v operation
ISL8200AM 14 fn8271.2 september 13, 2012 selection of the input capacitor the input filter capacitor should be based on how much ripple the supply can tolerate on the dc input line. the larger the capacitor, the less ripple expected, but consideration should be taken for the higher surge current during power-up. the ISL8200AM provides the soft-start function that controls and limits the current surge. the value of the input capacitor can be calculated by equation 4: where: c in(min) is the minimum input capacitance (f) required i o is the output current (a) d is the duty cycle (v o /v in ) v p-p(max) is the maximum peak-to-peak voltage (v) f s is the switching frequency (hz) in addition to the bulk capacitance, some low equivalent series inductance (esl) ceramic capacitance is recommended to decouple between the drain termin al of the high side mosfet and the source terminal of the low side mosfet. this is used to reduce the voltage ringing created by the switching current across parasitic circuit elements. output capacitors the ISL8200AM is designed for low output voltage ripple. the output voltage ripple and transien t requirements can be met with bulk output capacitors (c out ) with low enough equivalent series resistance (esr); the recommended esr is <10m ? . when the total esr is below 4m ? , a capacitor (c ff ) between 2.2nf-10nf is recommended; c ff is placed in parallel with rset, in between the vout and vout_set pin. c out can be a low esr tantalum capacitor, a low esr polymer capacitor or a ceramic capacitor. the typical capacitance is 330f and decoupled ceramic output capacitors are used per phase. the internally optimized loop compensation provides sufficient stability margins for all ceramic capacitor applications with a recommended total value of 300f per phase. additional output filtering may be needed if further reduction of output ripple or dynamic transient spike is required. using multiple phases the ISL8200AM can be easily conn ected in parallel with other ISL8200AM modules and current sh are providing an additional 10a per phase. for 2 phases, simply follow the schematic shown in figure 4. a rough summary sh ows that the modules share vin, vout, gnd and have their ishare pins tied together with a 10k ? resistor to ground (per phase). when using 3 phases or more, it is recommended that you add the following circuitry (see figure 24) to ensure proper startup. the ci rcuit shown in figure 24 ensures proper startup by injecting curren t into the ishare line until all phases are ready to start regula ting. for additional phases, the rc time constant, using r inc - and c g , might have to be adjusted to increase the turn on time of the pfet (qshr). for 3-4 phases, these are the values, r inc = 243k, r ph1 = 15k, q shr = small signal pfet, c g = 22nf). functional description initialization the ISL8200AM requires vcc and pvcc to be biased by a single supply. power-on reset (por) circuits continually monitor the bias voltages (pvcc and vcc) and the voltage at the en pin. the por function initiates soft-start operation 384 clock cycles after the en pin voltage is pulled to be above 0.8v; all input supplies exceed their por thresholds and the pll locking time expires. the enable pin can be used as a voltage monitor and to set desired hysteresis with an internal 30a sinking current going through an external resistor divider. the sinking current is disengaged after the system is enabled. this feature is especially designed for applications that require higher input rail por for better undervoltage protection. for example, in 12v applications, r up = 53.6k and r down = 5.23k will set the turn-on threshold (v en_rth ) to 10.6v and turn-off threshold (v en_fth ) to 9v, with 1.6v hysteresis (v en_hys ). these numbers are explained in figure 29 on page 15. during shutdown or fault conditions, the soft-start is quickly reset while ugate and lgate immediately change state (<100ns) upon the input dropping below por. soft-start the ISL8200AM has an internal digital pre-charged soft-start circuitry, which has a rise time inversely proportional to the switching frequency and is determined by a digital counter that increments with every pulse of the phase clock. the full soft-start time from 0v to 0.6v can be estimated by equation 5. c in min () i o d1d ? () ? v p-p max () f s ? --------------------------------------- ? = (eq. 4) figure 25. soft-start initialization logic isfetdrv (phase 2) isfetdrv (phase 3) isfetdrv (phase 1) add additional diodes per phase vcc (phase 1) ishare q shr r inc r ph1 d ph2 d ph2 c g figure 24. startup circuitry vcc por pvcc por en por soft-start high = above por; low = below por of module and 384 pll locking cycles t ss 2560 f sw ------------- - = (eq. 5)
ISL8200AM 15 fn8271.2 september 13, 2012 the ISL8200AM has the ability to work under a pre-charged output. the pwm outputs will not be fed to the drivers until the first pwm pulse is seen. the low side mosfet is held low for the first clock cycle to provide charge for the bootstrap capacitor. if the pre-charged output voltage is greate r than the final target level but less than the 113% setpoi nt, switching will not start until the output voltage is reduced to the target voltage and the first pwm pulse is generated. the maximum allowable pre-charged level is 113%. if the pre-charged level is above 113% but below 120%, the output will hiccup between 113% (lgate turns on) and 87% (lgate turns off) while en is pulled low. if the pre-charged load voltage is above 120% of the targeted output volt age, then the controller will be latched off and not be able to power-up. voltage feedforward the voltage applied to the ff pin is fed to adjust the sawtooth amplitude of the channel. the amplitude the sawtooth is set to is 1.25 times the corresponding ff voltage when the module is enabled. this configuration help s to maintain a constant gain (g m =v in ?d max / v ramp ) and input voltage to achieve optimum loop response over a wide input voltage range. the sawtooth ramp offset voltage is 1v (equal to 0.8v*1.25), and the peak of the sawtooth is limited to v cc - 1.4v. with v cc = 5.4v, the ramp has a maximum peak-t o-peak amplitude of v cc - 2.4v (equal to 3v); so the feed-forward voltage effective range is typically 3x as the ramp amplitude ranges from 1v to 3v. a 384 cycle delay is added after the system reaches its rising por and prior to the soft-start. the rc timing at the ff pin should be sufficiently small to ensure that the input bus reaches its static state and the internal ra mp circuitry stabilizes before soft-start. a large rc could cause the internal ramp amplitude not to synchronize with the input bus voltage during output start-up or when recovering from faults. a 1nf capacitor is recommended as a starting valu e for typical applications. the voltage on the ff pin needs to be above 0.8v prior to soft-start and during pwm switching to ensure reliable regulation. in a typical application, ff pin can be shorted to the en pin. vout target voltage 0.0v t ss 2560 f sw ------------- - first pwm pulse -100mv figure 26. soft-start with v out = 0v ss settling at vref + 100mv t ss_dly 384 f sw ---------- init. vout vout target voltage first pwm pulse -100mv ss settling at vref + 100mv figure 27. soft-start with v out < target voltage ov = 113% vout target voltage first pwm pulse figure 28. soft-start with v out below ov but above final target voltage figure 29. simplified enable and voltage feedforward circuit 0.8v i en_hys = 30 a r up r down en_por r down r up v ? en_ref v en_fth v en_ref ? ------------------------------------------------------ - = v en_fth v en_rth v en_hys ? = vin g ramp = 1.25 limiter sawtooth amplitude v ramp max(v cc_ff g ramp , vcc - 1.4v - v ramp_offset ) = ( v ramp ) en ov, ot, oc, and pll locking faults r up v en_hys nxi en_hys ------------------------------ = system delay v cc_ff vcc 0.8v v ramp_offset = 1.0v vcc - 1.4v lower limit upper limit (ramp offset) where n is number of en pins connected together v cc_ff max(0.8v, v ff ) = ff
ISL8200AM 16 fn8271.2 september 13, 2012 power good the power-good comparators monitor the voltage on the internal vmon1 pin. the trip points are shown in figure 30. pgood will not be asserted until after the completion of the soft-start cycle. the pgood pulls low upon both en?s disabling it or the internal vmon1 pin?s voltage is out of th e threshold window. pgood will not be asserted until after the completion of the soft-start cycle. pgood will not pull low until the fault is present for three consecutive clock cycles. the uv indication is not enabled until the end of soft-start. in a uv event, if the output drops below -13% of the target level due to some reason (cases when en is not pulled low) other than ov, oc, ot, and pll faults, pgood will be pulled low. current share the iavg_cs is the current of the module. ishare and iset pins source a copy of iavg_cs with 15a offset, i.e., the full scale will be 126a. the share bus voltage (v ishare ) set by an external resistor (r ishare = r iset /nctrl) represents the average current of all active modules. the voltage (v iset ) set by r iset represents the average current of the correspo nding module and is compared with the share bus (v ishare ). the current share error signal (icsh_er) is then fed into the current correction block to adjust each module?s pwm pulse accordingly. the current share function provides at least 10% overall accuracy between ics, up to 3 phases. the current share bus works for up to 6-phase. figure 4 further illustrates the current sharing aspects of the ISL8200AM. when there is only one module in the system, the iset and ishare pins can be shorted together and grounded via a single resistor to ensure zero share error - a resistor value of 5k (paralleling 10k on iset and ishare) will allow operation up to the ocp level. overvoltage protection (ovp) the overvoltage (ov) protection indication circuitry monitors the voltage on the internal vmon1 pin. ov protection is active from th e beginning of soft-start. an ov condition (>120%) would latch the ic off (the high-side mosfet to latch off permanently; the low-side mosfet turns on immediately at the time of ov trip and then turns off permanently after the output vo ltage drops below 87%). the en and pgood are also latched low at ov event. the latch condition can be reset only by recycling vcc. there is another non-latch ov protection (113% of target level). at the condition of en low an d the output over 113% ov, the lower side mosfet will turn on until the output drops below 87%. this is to protect the overall power trains in case of a single channel of a multi-module system detecting ov. the low-side mosfet always turns on at the conditions of en = low and the output voltage above 113% (all en pins are tied together) and turns off after the output drops below 87%. thus, in a high phase count application (multi-module mode), all cascaded modules can latch off simultaneously via the en pins (en pins are tied together in multiphase mode), and each ic shares the same sink current to reduce the stress and eliminate the bouncing among phases. over-temperature protection (otp) when the junction temperature of the ic is greater than +150c (typically), en pin will be pulled low to inform other cascaded channels via their en pins. all connected ens stay low and release after the ic?s junction temperature drops below +125c (typically), a +25c hysteresis (typically). overcurrent protection (ocp) the ocp function is enabled at startup. the load current sampling ics1 is sensed by sampling the voltage across q2 mosfet r ds(on) during turn on through the resistor between ocset and phase pin. ic1 is compared with the channel overcurrent limit ?111a ocp? comparator, and waits 7-cycles before ocp condition is declared. the module?s output current (ics1) plus a fixed internal 15a offset forms a voltage (v ishare ) across the external resistor, r ishare . v ishare is compared with a precision internal 1.2v threshold for a second method to detect ocp condition. multi-module operation can be achieved by connecting the ishare pin of two or more modules together. in multi-module operation the voltage on the ishare pin correlates to the average current of all active chan nels. the output current of each module in multi-module operation is compared to a precise 1.2v threshold to determine the overcu rrent condition. additionally, each module has an overcurrent trip point of 111a with 7-cycle delay. note that it is not necessary for the r ishare to be scaled to trip at the same level as the 111a ocp comparator. typically the ishare pin average current protection level should be higher than the phase current protection level. with an internal r isen-in of 2.2k ? , the ocp level is set to the default value. to lower the ocp level, an external r isen-ex is connected between ocset and ph ase pin. the relationships between the external r isen-ex values and the typical output current i out(max) ocp levels for ISL8200AM are shown in figure 30. power-good threshold window -13% -9% v ref +9% +13% vmon1 end of ss1 and pgood channel 1 uv/ov +20% pgood pgood latch off after 120% ov
ISL8200AM 17 fn8271.2 september 13, 2012 figures 31 through 33. it is important to note that the ocp level shown in these graphs is the average output current and not the inductor ripple current. in a high input voltage, high outp ut voltage application, such as 20v input to 5v output, the inductor ripple becomes excessive due to the fixed internal inductor value. in such applications, the output current will be limited from the rating to approximately 70% of the module?s rated current. when ocp is triggered, the controller pulls en low immediately to turn off ugate and lgate. for overload and hard short conditions, the overcurrent protection reduces the regulator rms output current much less than full load by putting the controller into hiccup mode. a delay time, equal to 3 soft-start intervals, is entered to allow the disturbance to be cleared out. after the delay time, the controller then initiates a soft-start interval. if the output voltage comes up and returns to the regulation, pgood transitions high. if the oc trip is exceeded during the soft-start interval, the controller pulls en low again. the pgood signal will remain low and the soft-start interval will be allowed to expire. another soft-start interval will be initiated after the delay interval. if an overcurrent trip occurs again, this same cycle repeats until the fault is removed. fault handshake in a multi-module system, with the en pins wired or?ed together, all modules can immediately turn off, at one time, when a fault condition occurs in one or more modules. a fault would pull the en pin low, disabling all the modules and therefore not creating current bounce. thus, no single channel would be over stressed when a fault occurs. since the en pins are pulled down under fault conditions, the pull-up resistor (r up ) should be scaled to sink no more than 5ma current from en pin. essentially, the en pins canno t be directly connected to vcc. oscillator the oscillator is a sawtooth waveform, providing for leading edge modulation with 350ns minimum dead time. the oscillator (sawtooth) waveform has a dc offset of 1.0v. each channel?s peak-to-peak of the ramp amplitud e is set to be proportional to the voltage applied to its corresponding ff pin. frequency synchronization and phase lock loop the fsync_in pin has two primar y capabilities: fixed frequency operation and synchronized freq uency operation. by tying a resistor (rfs) to pgnd1 from the fsync_in pin, the switching frequency can be set at any frequency between 700khz and 1.5mhz. the ISL8200AM has an integrated 59k ? resistor between fsync_in and pgnd1, which sets the default frequency to 700khz. the frequency setting curve shown in figure 34 is provided to assist in selecting an externally connected resistor rfs-ext between fsync_in and pg nd1 to increase the switching frequency. figure 31. 5v in figure 32. 12v in figure 33. 20v in r sen (k ? ) ocp (a) 0 2 4 6 8 10 12 14 16 0 5 10 15 20 1.8v out 1.2v out 2.5v out r sen (k ? ) ocp (a) 0 2 4 6 8 10 12 14 16 0 1020304050 1.8v out 2.5v out 1.2v out 5.0v out r sen (k ? ) ocp (a) 0 2 4 6 8 10 12 14 16 020406080100 1.8v out 2.5v out 1.2v out 5.0v out
ISL8200AM 18 fn8271.2 september 13, 2012 by connecting the fsync_in pin to an external square pulse waveform (such as the clkout signal, typically 50% duty cycle from another ISL8200AM), the ISL8200AM will synchronize its switching frequency to the fundamental frequency of the input waveform. the voltage range on the fsync_in pin is v cc /2 to v cc . the frequency synchronization feature will synchronize the leading edge of the clkout signal with the falling edge of channel 1?s pwm clock signal. clkout is not available until the pll locks. the locking time is typically 210s for f sw = 700khz. en is not released for a soft-start cycle until fsync_in is stabilized and the pll is in locking. it is reco mmended to connect all en pins together in multiphase configuration. the loss of a synchronization signal for 13 clock cycles causes the ic to be disabled until the pll returns locking, at which point a soft-start cycle is initiated and normal operation resumes. holding fsync_in low will disable the ic. setting relative phase-shift on clkout depending upon the voltage level at ph_cntrl, set by the vcc resistor divider output, the is l8200am operates with clkout phase shifted, as shown in table 2. the phase shift is latched as v cc raises above por so it cannot be changed on the fly. layout guide to achieve stable operation, low losses, and good thermal performance, some layout considerations are necessary, which are illustrated in figures 35 and 36. ? the ground connection between pgnd1 (pin 15) and pgnd (pin 18) should be a solid ground plane under the module. ? place a high frequency ceramic capacitor between (1) pvin and pgnd (pin 18) and (2) a 10f between pvcc and pgnd1 (pin 15) as close to the module as possible to minimize high frequency noise. high frequenc y ceramic capacitors close to the module between vout and pgnd will help to minimize noise at the output ripple. ? use large copper areas for power path (pvin, pgnd, vout) to minimize conduction loss and thermal stress. also, use multiple vias to connect the power planes in different layers. ? keep the trace connection to the feedback resistor short. ? use remote sensed traces to the regulation point to achieve a tight output voltage regulation , and keep them in parallel. route a trace from vsen_rem- to a location near the load ground, and a trace from feedback resistor to the point-of-load where the tight output voltage is desire. ? avoid routing any sensitive signal traces, such as the vout and vsenrem- sensing point near the phase pin or any other noise-prone areas. ? fsync_in is a sensitive pin. if it is not used for receiving an external synchronization signal, then keep the trace connecting to the pin short. a bypass capacitor value of 100pf, connecting between fsync_in pin and gnd1, can help to bypass the noise sensitivity on the pin. the recommended layout consider ations for operating multiple modules in parallel follows the single-phase guidelines as well as these additional points: ? orient vout towards the load on the same layer and connect with thick direct copper etch directly to minimize the loss. ? place modules such that pins 1-11 point away from power pads (pd1-4) so that signal busses (en, ishare, clkout-to-fsyncin) can be routed without going under the module. run them along the perimeter as in figure 36. ? keep remote sensing traces separate, and connect only at the regulation point. four separa te traces for vsen_rem- and rfbt (which stands for remote feedback) as in the example in figure 36. figure 34. rfs-ext vs switching frequency table 2. decoding ph_cntrl range phase for clkout wrt channel 1 required ph_cntrl <29% of v cc -60 15% v cc 29% to 45% of v cc 90 37% v cc 45% to 62% of v cc 120 53% v cc 62% to v cc 180 v cc 700 800 900 1000 1100 1200 1300 1400 1500 0 100 200 300 400 rfs-ext (k ? ) switching frequency (khz) to vout cen cpvcc cin cout rfbt to load gnd figure 35. recommended layout for single phase setup v out pgnd pv in
ISL8200AM 19 fn8271.2 september 13, 2012 to vout cen cpvcc cin cout rfbt to load gnd clkout to fsync_in en ishare to vout cen cpvcc cin cout rfbt to load gnd figure 36. recommended layout for dual phase setup
ISL8200AM 20 fn8271.2 september 13, 2012 thermal considerations empirical power loss curves, shown in figures 37 to 40, along with ja from thermal modeling analysis can be used to evaluate the thermal consideration for the module. the derating curves are derived from the maximum power allowed while maintaining the temperature below the maximum junction temperature of +125c. in actual application, other heat sources and design margin should be considered. package description the structure of the ISL8200AM belongs to the quad flat-pack no-lead package (qfn). this ki nd of package has advantages, such as good thermal and electric al conductivity, low weight and small size. the qfn package is applicable for surface mounting technology and is being more readily used in the industry. the ISL8200AM contains several types of devices, including resistors, capacitors, inductors and control ics. the ISL8200AM is a copper lead-frame based package with exposed copper thermal pads, which have good electrical and thermal conductivity. the copper lead frame and multi component assembly is overmolded with polymer mold compound to protect these devices. the package outline and typical pcb layout pattern design and typical stencil pattern design are shown in the package outline drawing l23.15x15 on page 23. the module has a small size of 15mm x 15mm x 2.2mm. figure 41 shows typical reflow profile parameters. these guidelines are general design rules. users could modify parameters acco rding to their application. pcb layout pattern design the bottom of ISL8200AM is a lead-frame footprint, which is attached to the pcb by surface mounting process. the pcb layout pattern is shown in the package outline drawing l23.15x15 on page 23. the pcb layout pattern is essentially 1:1 with the qfn exposed pad and i/o termination dimensions, except for the pcb lands being a slightly extended distance of 0.2mm (0.4mm max) longer than the qfn terminations, which allows for solder filleting around the periphery of the package. this ensures a more complete an d inspectable solder joint. the thermal lands on the pcb layout should match 1:1 with the package exposed die pads. thermal vias a grid of 1.0mm to 1.2mm pitch thermal vias, which drops down and connects to buried copper plane(s), should be placed under the thermal land. the vias should be from 0.3mm to 0.33mm in diameter with the barrel plated with 1.0 ounce copper. although adding more vias (by decreasing via pitch) will improve the thermal performance, diminishing returns will be seen as more figure 37. power loss vs load current (5v in ) 0 lfm for various output voltages figure 38. derating curve (5v in ) 0 lfm for various output voltages figure 39. power loss vs load current (12v in ) 0 lfm for various output voltages figure 40. derating curve (12v in ) 0 lfm for various output voltages 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0610 load current (a) loss (w) 8 4 2 0.8v 1.5v 3.3v 0 2 4 6 8 10 12 60 70 80 90 100 110 ambient temperature (c) max load current (a) 0.8v 1.5v 3.3v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 010 load current (a) loss (w) 0.8v 1.5v 2.5v 3.3v 5.0v 2468 0 2 4 6 8 10 12 60 70 80 90 100 110 ambient temperature (c) max load current (a) 0.8v 1.5v 2.5v 3.3v 5.0v
ISL8200AM 21 fn8271.2 september 13, 2012 and more vias are added. simply use as many vias as practical for the thermal land size and your board design rules allow. stencil pattern design reflowed solder joints on the perimeter i/o lands should have about a 50m to 75m (2mil to 3m il) standoff height. the solder paste stencil design is the first step in developing optimized, reliable solder joins. stencil aperture size to land size ratio should typically be 1:1. the aperture width may be reduced slightly to help prevent solder bridging between adjacent i/o lands. to reduce solder paste volume on the larger thermal lands, it is recommended that an array of smaller apertures be used instead of one large aperture. it is recommended that the stencil printing area cover 50% to 80% of the pcb layout pattern. a typical solder stencil pattern is shown in the package outline drawing l23.15x15 on page 24. the gap width between pad to pad is 0.6mm. the user should consider the symmetry of the whole stencil pattern when designing its pads. a laser cut, stainless steel stencil with electropolished trapezoidal walls is recommended. electropolishing ?smooths? the aperture walls resulting in reduced surface friction and better paste release, which reduces voids. using a trapezoidal section aperture (tsa) also promotes paste release an d forms a "brick like" paste deposit that assists in firm co mponent placement. a 0.1mm to 0.15mm stencil thickness is recommended for this large pitch (1.3mm) qfn. reflow parameters due to the low mount height of the qfn, "no clean" type 3 solder paste per ansi/j-std-005 is re commended. nitrogen purge is also recommended during reflow. a system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the qfn. the profile given in figure 41 is provided as a guideline, to be customized for varying manufacturing practices and applications. figure 41. typical reflow profile 0 300 100 150 200 250 350 0 50 100 150 200 250 300 temperature (c) duration (s) slow ramp (3c/s max) and soak from +100c to +180c for 90s~120s ramp rate 1.5c from +70c to +90c peak temperature +230c~+245c; typically 60s-70s above +220c keep less than 30s within 5c of peak temp.
ISL8200AM 22 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8271.2 september 13, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL8200AM to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change september 13, 2012 fn8271.2 initial release.
ISL8200AM 23 fn8271.2 september 13, 2012 package outline drawing l23.15x15 23 lead quad flat no-lead plastic package (punch qfn) rev 3, 10/10 bottom view side view top view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.2; the configuration of the pin #1 identifier is optional, but must be 3. either a mold or mark feature. 2. dimensions are in millimeters. 1. notes: body tolerance 0.2mm 1.02 7x 1.9 0.05 11x 1.85 0.05 4.38 5.82 2.2 13.8 9.9 4.7 4.8 2.0 0.82 3.22 0.2 x4 h ab 35x 0.5 ab h 0.05 m 7x 0.8 18x 0.75 11 10 9 8 7 6 5 4 3 2 1 16 17 19 22 21 20 23 14 13 12 15 (35x 0.40) 15.00.2 15.00.2 s 0.2 s 0.05 2.2 0.2 8 all around s 0.25 b 11x 0.7 0.2 x4 ab h 10x 1.1 0.1 18x 1.3 0.1 3x 2.6 18 3 4 2 1 5 6 7 8 10 9 11 12 13 14 15 16 19 21 18 17 22 20 2.36 2.28 0.90 3.4 4.7 3.4 4.26 0.8 1.34 23 a 15.80.2 15.80.2
ISL8200AM 24 fn8271.2 september 13, 2012 stencil pattern with square pads-1 typical recomme nded land pattern stencil pattern with square pads-2 0.00 5.80 5.50 6.73 4.68 4.38 2.33 0.52 0.82 2.82 3.67 1.53 6.52 2.28 0.28 0.98 0.00 6.82 4.92 4.22 8.10 6.48 5.48 4.88 4.18 3.58 0.32 1.02 1.62 2.32 2.92 3.62 2.88 1.58 8.10 5.52 8.09 6.78 0.83 2.83 4.13 3.43 2.13 1.53 3.67 1.77 0.00 1.07 2.37 3.07 5.72 4.37 4.97 0.13 4.13 6.03 6.73 2.13 2.83 3.43 1.48 0.88 3.07 1.07 0.00 0.60 2.37 1.77 4.97 5.67 4.37 3.67 6.11 5.18 6.03 5.78 0.77 2.48 4.08 4.68 2.98 3.58 0.78 1.38 1.88 0.32 0.28 0.00 3.62 1.92 1.47 3.02 2.52 5.82 5.22 4.72 4.12 6.07 0.93 5.68 6.48 4.03 4.88 4.83 3.05 2.75 0.00 0.13 6.48 2.23 4.58 4.28 1.48 0.88 0.60 0.00 1.83 6.23 3.88 4.18 4.69 0.82 0.52 1.53 0.00 2.87 3.17 6.52 4.99 4.64 5.58 6.88 8.15 2.18 1.68 0.00 3.52 3.02 5.62 8.15 4.03 1.82 4.18 8.14 6.88 4.68 0.78 1.02 0.00 5.72 3.62 2.32 3.12 4.42 4.92 5.83 5.98 4.73 5.13 2.32 2.08 5.53 6.88 8.14 5.03 0.18 0.78 1.58 1.82 0.65 0.00 1.87 0.73 2.53 3.63 2.93 1.43 1.83 0.37 0.33 0.00 0.77 1.47 6.06 5.72 3.62 3.12 4.42 4.92 5.17 3.67 2.57 2.97 4.07 4.77 6.02 5.87 1 23 tag

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